1 motorola tmos power mosfet transistor device data product preview tmos e-fet . ? high energy power fet d 2 pak-sl straight lead n?channel enhancement?mode silicon gate this high voltage mosfet uses an advanced termination scheme to provide enhanced voltage?blocking capability without degrading performance over time. in addition, this advanced tmos e?fet is designed to withstand high energy in the avalanche and commutation modes. the new energy efficient design also offers a drain?to?source diode with a fast recovery time. designed for high voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? robust high voltage termination ? avalanche energy specified ? source?to?drain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? short heatsink tab manufactured e not sheared ? specially designed leadframe for maximum power dissipation maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?source voltage v dss 800 vdc drain?gate voltage (r gs = 1.0 m w ) v dgr 800 vdc gate?source voltage e continuous gate?source voltage e non?repetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current e continuous drain current e continuous @ 100 c drain current e single pulse (t p 10 m s) i d i d i dm 4.0 2.9 12 adc apk total power dissipation derate above 25 c total power dissipation @ t a = 25 c, when mounted with the minimum recommended pad size p d 125 1.0 2.5 watts w/ c watts operating and storage temperature range t j , t stg ? 55 to 150 c single pulse drain?to?source avalanche energy e starting t j = 25 c (v dd = 100 vdc, v gs = 10 vdc, i l = 8.0 apk, l = 10 mh, r g = 25 w ) e as 320 mj thermal resistance e junction to case thermal resistance e junction to ambient thermal resistance e junction to ambient, when mounted with the minimum recommended pad size r q jc r q ja r q ja 1.0 62.5 50 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice. e?fet is a trademark of motorola, inc. tmos is a registered trademark of motorola, inc. preferred devices are motorola recommended choices for future use and best overall value. order this document by MTB4N80E1/d motorola semiconductor technical data MTB4N80E1 tmos power fet 4.0 amperes 800 volts r ds(on) = 3.0 ohm motorola preferred device case 418c?01, style 2 d 2 pak?sl d s g ? ? motorola, inc. 1997
MTB4N80E1 2 motorola tmos power mosfet transistor device data electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?source breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 800 e e 1.02 e e vdc mv/ c zero gate voltage drain current (v ds = 800 vdc, v gs = 0 vdc) (v ds = 800 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 10 100 m adc gate?body leakage current (v gs = 20 vdc, v ds = 0) i gss e e 100 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 e 3.0 7.0 4.0 e vdc mv/ c static drain?source on?resistance (v gs = 10 vdc, i d = 2.0 adc) r ds(on) e 1.95 3.0 ohm drain?source on?voltage (v gs = 10 vdc) (i d = 4.0 adc) (i d = 2.0 adc, t j = 125 c) v ds(on) e e 8.24 e 12 10 vdc forward transconductance (v ds = 15 vdc, i d = 2.0 adc) g fs 2.0 4.3 e mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss e 1320 2030 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss e 187 400 reverse transfer capacitance f = 1 . 0 mhz) c rss e 72 160 switching characteristics (2) turn?on delay time t d(on) e 13 30 ns rise time (v dd = 400 vdc, i d = 4.0 adc, v gs = 10 vdc t r e 36 90 turn?off delay time v gs = 10 vdc, r g = 9.1 w ) t d(off) e 40 80 fall time r g 9.1 w ) t f e 30 75 gate charge (s fi 8) q t e 36 80 nc (see figure 8) (v ds = 400 vdc, i d = 4.0 adc, q 1 e 7.0 e (v ds 400 vdc , i d 4 . 0 adc , v gs = 10 vdc) q 2 e 16.5 e q 3 e 12 e source?drain diode characteristics forward on?voltage (1) (i s = 4.0 adc, v gs = 0 vdc) (i s = 4.0 adc, v gs = 0 vdc, t j = 125 c) v sd e e 0.812 0.7 1.5 e vdc reverse recovery time (s fi 14) t rr e 557 e ns (see figure 14) (i s = 4.0 adc, v gs = 0 vdc, t a e 100 e (i s 4 . 0 adc , v gs 0 vdc , di s /dt = 100 a/ m s) t b e 457 e reverse recovery stored charge q rr e 2.33 e m c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d e 4.5 e nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s e 7.5 e nh (1) pulse test: pulse width 300 m s, duty cycle 2%. (2) switching characteristics are independent of operating junction temperature.
MTB4N80E1 3 motorola tmos power mosfet transistor device data typical electrical characteristics r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) v ds , drain-to-source voltage (volts) figure 1. on?region characteristics i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics i d , drain current (amps) figure 3. on?resistance versus drain current and temperature i d , drain current (amps) figure 4. on?resistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. on?resistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) t j = 25 c 048121620 7 2 6 10 14 18 3 5 v 6 v v ds 10 v 2.0 2.8 3.6 4.4 5.2 2.4 3.2 4.0 4.8 t j = -55 c 25 c 100 c t j = 25 c v gs = 10 v 15 v 1.8 2.4 2.1 v gs = 0 v 0 200 400 1 100 10000 100 300 600 500 25 c t j = 125 c 13 7 0.6 2.2 3.8 4.6 3.0 1.4 5 t j = 100 c 25 c -55 c v gs = 10 v -50 0.2 0.6 1.0 1.8 2.2 -25 0 25 50 75 100 125 150 v gs = 10 v i d = 2 a 4 v 5 1 1000 2.3 2.5 2.6 2.2 2.0 1.4 6 2 8 4 i d , drain current (amps) 5.6 24 8 6 1.9 10 800 700 0 7 3 5 1 6 2 8 4 0 13 7 5 24 8 6 100 c v gs = 10 v
MTB4N80E1 4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are deter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculat- ing rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis- tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when cal- culating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements com- plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. the resistive switching time variation versus gate resis- tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely op- erated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7a. capacitance variation figure 7b. high voltage capacitance variation v ds , drain-to-source voltage (volts) 10 100 1000 10000 100 10 1 c, capacitance (pf) 10 0 10152025 2800 2000 1200 400 0 v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 1600 800 55 v gs = 0 v t j = 25 c 2400 1000 c oss c iss c iss c iss c rss c rss c oss c rss
MTB4N80E1 5 motorola tmos power mosfet transistor device data q g , total gate charge (nc) drain?to?source diode characteristics v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 100 10 t, time (ns) figure 8. gate?to?source and drain?to?source voltage versus total charge v gs , gate-to-source voltage (volts) v ds , drain-to-source voltage (volts) 01218 i d = 4 a t j = 25 c v ds v gs q1 q2 qt 36 10 6 2 0 8 4 500 400 300 100 200 v dd = 400 v i d = 4 a v gs = 10 v t j = 25 c t f t d(off) t d(on) 0.50 0.70 0.78 0 4.0 0.66 0.74 0 0.82 0.58 0.54 0.62 3.2 2.4 1.6 0.8 q3 62430 t r 3.6 2.8 2.0 1.2 0.4 v gs = 0 v t j = 25 c safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is for- ward biased. curves are based upon maximum peak junc- tion temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance?gener- al data and its use.o switching between the off?state and the on?state may tra- verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power aver- aged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reli- able operation, the stored energy from circuit inductance dis- sipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a con- stant. the energy rating decreases non?linearly with an in- crease of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain? to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous cur- rent (i d ), in accordance with industry custom. the energy rat- ing must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at cur- rents below rated continuous i d can safely be assumed to equal the values indicated.
MTB4N80E1 6 motorola tmos power mosfet transistor device data safe operating area figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 0 0.5 1 1.5 2.0 2.5 3 25 50 75 100 125 150 t a , ambient temperature ( c) p d , power dissipation (watts) figure 15. d 2 pak power derating curve r q ja = 50 c/w board material = 0.065 mil fr?4 mounted on the minimum recommended footprint collector/drain pad size 450 mils x 350 mils 0.1 1.0 1000 100 r ds(on) limit thermal limit package limit 0.01 100 10 10 t j , starting junction temperature ( c) e as , single pulse drain-to-source figure 12. maximum avalanche energy versus starting junction temperature v ds , drain-to-source voltage (volts) figure 11. maximum rated forward biased safe operating area avalanche energy (mj) i d , drain current (amps) 0.1 t, time (s) figure 13. thermal response r(t), normalized effective transient thermal resistance r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 25 150 0 1.0e-05 1.0e-04 1.0e-02 0.1 1.0 0.01 1.0e-03 1.0e-01 1.0e+00 0.2 0.1 0.05 0.02 single pulse d = 0.5 350 v gs = 20 v single pulse t c = 25 c 50 100 125 75 50 200 150 100 i d = 4 a 1.0 300 250 0.01 dc 100 m s 10 m s 1ms 10ms 1.0e+01
MTB4N80E1 7 motorola tmos power mosfet transistor device data package dimensions case 418c?01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 2: pin 1. gate 2. drain 3. source 4. drain ?t? w g k a c e v j h 123 4 seating plane d 3 pl dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 s 0.276 ref 7.00 ref v 0.045 0.055 1.14 1.40 w 0.423 0.462 10.75 11.75 ?b? m b m 0.13 (0.005) t s f f 0.039 ref 1.00 ref k 0.280 0.360 7.11 9.14
MTB4N80E1 8 motorola tmos power mosfet transistor device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operatin g parameters, including at ypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a s ituation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4?32?1, p.o. box 5405, denver, colorado 80217. 1?303?675?2140 or 1?800?441?2447 nishi?gotanda, shinagawa?ku, tokyo 141, japan. 81?3?548 7?8488 customer focus center: 1?800?521?6274 mfax ? : rmfax0@email.sps.mot.com ? t ouchtone 1?602?244?6609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system ? us & canada only 1?800?774?1848 51 ting kok road, tai po, n.t., hong kong. 852?26629298 ? http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ MTB4N80E1/d ?
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